Digital logic design : a rigorous approach / Guy Even and Moti Medina

PART I: PRELIMINARIES;
CHAPTER 1 Sets and Functions;
1.1 SETS;
1.2 RELATIONS AND FUNCTIONS;
1.3 BOOLEAN FUNCTIONS;
1.3.1 Truth Tables;
1.4 COMMUTATIVE AND ASSOCIATIVE BINARY OPERATIONS;

CHAPTER 2 Induction and Recursion;
2.1 INDUCTION;
2.2 RECURSION.
2.3 APPLICATION: ONE-TO-ONE AND ONTO FUNCTIONS

CHAPTER 3 Sequences and Series;
3.1 SEQUENCES;
3.2 SERIES;

CHAPTER 4 Directed Graphs;
4.1 DEFINITIONS;
4.2 TOPOLOGICAL ORDERING;
4.3 LONGEST PATH IN A DAG;
4.4 ROOTED TREES;

CHAPTER 5 Binary Representation;
5.1 DIVISION AND MODULO;
5.2 BITS AND STRINGS;
5.3 BIT ORDERING;
5.4 BINARY REPRESENTATION;
5.5 COMPUTING A BINARY REPRESENTATION;
5.6 MORE ON UNIQUE BINARY REPRESENTATION;

CHAPTER 6 Propositional Logic;
6.1 BOOLEAN FORMULAS;
6.2 TRUTH ASSIGNMENTS;
6.3 SATISFIABILITY AND LOGICAL EQUIVALENCE;
6.4 INTERPRETING A BOOLEAN FORMULA AS A FUNCTION.
6.5 SUBSTITUTION
6.6 COMPLETE SETS OF CONNECTIVES;
6.7 IMPORTANT TAUTOLOGIES;
6.8 DE MORGAN'S LAWS;
6.8.1 NEGATION NORMAL FORM;

CHAPTER 7 Asymptotics;
7.1 ORDER OF GROWTH RATES;
7.2 RECURRENCE EQUATIONS;

CHAPTER 8 Computer Stories: Big Endian versusLittle Endian;


PART II: COMBINATIONAL CIRCUITS;
CHAPTER 9 Representations of Boolean Functions by Formulas;
9.1 SUM OF PRODUCTS;
9.2 PRODUCT OF SUMS;
9.3 THE FINITE FIELD GF(2);
9.3.1 Polynomials Over GF(2);
9.4 SATISFIABILITY;
9.5 RELATION TO P VERSUS NP;
9.6 MINIMIZATION HEURISTICS;
9.6.1 Basic Terminology and Properties.
9.6.2 The Implicants' Graph
9.6.3 Essential Prime Implicants;
9.6.4 Optimality Conditions;
9.6.5 The Quine-McCluskey Heuristic;
9.6.6 Karnaugh Maps;

CHAPTER 10 The Digital Abstraction;
10.1 TRANSISTORS;
10.2 A CMOS INVERTER;
10.3 FROM ANALOG SIGNALS TO DIGITAL SIGNALS;
10.4 TRANSFER FUNCTIONS OF GATES;
10.5 THE BOUNDED-NOISE MODEL;
10.6 THE DIGITAL ABSTRACTION IN THE PRESENCE OF NOISE;
10.6.1 Input and Output Signals; 10.6.2 Redefining the Digital Interpretation of Analog Signals;
10.7 STABLE SIGNALS;
10.8 SUMMARY;

CHAPTER 11 Foundations of Combinational Circuits.
11.1 COMBINATIONAL GATES: AN ANALOG APPROACH
11.2 BACK TO THE DIGITAL WORLD;
11.2.1 Example;
11.3 COMBINATIONAL GATES;
11.4 WIRES AND NETS;
11.5 COMBINATIONAL CIRCUITS;
11.6 PROPERTIES OF COMBINATIONAL CIRCUITS;
11.7 SIMULATION AND DELAY ANALYSIS;
11.8 COMPLETENESS;
11.9 COST AND PROPAGATION DELAY;
11.10 EXAMPLE: RELATIVE GATE COSTS AND DELAY;
11.11 SEMANTICS AND SYNTAX;
11.12 SUMMARY;

CHAPTER 12 Trees;
12.1 ASSOCIATIVE BOOLEAN FUNCTIONS;
12.2 TREES OF ASSOCIATIVE BOOLEAN GATES;
12.2.1 Cost Analysis;
12.2.2 Delay Analysis;
12.3 OPTIMALITY OF TREES;
12.3.1 Definitions

Includes bibliographical reference and index